Type of Document Master's Thesis Author Thankachan, Shibi Author's Email Address helloshibi@yahoo.com URN etd-12012006-104849 Title 64 x 64 Bit Multiplier Using Pass Logic Degree Master of Science Department Computer Science Advisory Committee
Advisor Name Title A. P. Preethy Committee Chair Michael Weeks Committee Member Saeid Belkasim Committee Member Keywords
- Multiplier
- Algorithm
- Wallace Tree
- Adder
Date of Defense 2006-12-20 Availability unrestricted Abstract ABSTRACT
Due to the rapid progress in the field of VLSI, improvements in speed, power and area are quite evident. Research and development in this field are motivated by growing markets of portable mobile devices such as personal multimedia players, cellular phones, digital camcorders and digital cameras. Among the recently popular logic families, pass transistor logic is promising for low power applications as compared to conventional static CMOS because of lower transistor count. This thesis proposes four novel designs for Booth encoder and selector logic using pass logic principles. These new designs are implemented and used to build a 64 x 64-bit multiplier. The proposed Booth encoder and selector logic are competitive with the existing and shows substantial reduction in transistor count. It also shows improvements in delay when compared to two of the three published works.
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